Santa Clara, CA, United States of America

Vinod Robert Purayath

This inventor holds 75 USPTO granted patents and 3 published patent applications and 2 EPO patents, primarily in 3D NAND Technology (CPC class H01L). Top assignees: Sandisk Technologies Inc., Applied Materials, Inc., Sandisk Corporation. Active years: 2009-2020.

USPTO Granted Patents = 75 

% Patents Active = 62.7

 

Average Co-Inventor Count = 3.5

ph-index = 20

Forward Citations = 2,445(Granted Patents)

Forward Citations (Not Self Cited) = 2,305(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Milpitas, CA (US) (2015)
  • Santa Clara, CA (US) (2009 - 2017)
  • Cupertino, CA (US) (2015 - 2019)
  • Los Gatos, CA (US) (2015 - 2020)

Company Filing History:


Years Active: 2009-2020

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Areas of Expertise:
3D NAND Structure
Non-Volatile Memory
Air Gap Isolation
Memory Cell Structures
Charge-Trap Layer
Resistance-Switching Cell
Integrated Bit-Line
Floating Gate
Vertical Gate Separation
Copper Interconnects
Nanodot Enhanced Memory
Memory Fabrication
75 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Vinod Robert Purayath

Introduction

Vinod Robert Purayath, based in Santa Clara, CA, is a prolific inventor recognized for his significant contributions to the field of memory technology. With a remarkable portfolio of 75 patents, Purayath has been at the forefront of innovations that enhance nonvolatile memory solutions.

Latest Patents

Among his latest patented innovations are groundbreaking methods and apparatus for fabricating three-dimensional NAND structures. His work on nonvolatile memory cells involves a sophisticated approach that includes depositing alternating layers of silicon oxide and silicon nitride, alongside intricate manipulation of amorphous silicon layers. This process not only maintains the integrity of the memory cell structure but also optimally positions silicon nitride and silicon oxide for enhanced performance.

Another notable patent revolves around 3D flash memory cells designed to minimize cross-cell electrical tunneling. Purayath’s methods for manufacturing these cells utilize a compound floating gate positioned between silicon oxide slabs, significantly reducing the quantum probability of electron tunneling. The inclusion of a high work function nanocrystalline metal within the floating gate is a key advancement, allowing for more precise manufacturing and reliability of memory cells.

Career Highlights

Vinod Robert Purayath has held key positions in esteemed companies such as SanDisk Technologies Inc. and Applied Materials, Inc. His tenure in these organizations has enabled him to develop state-of-the-art memory technologies, contributing to the advancement of data storage solutions in the industry.

Collaborations

Throughout his career, Purayath has collaborated with several prominent figures within the tech industry. Notably, he has worked alongside colleagues such as James K. Kai and George Matamis, exchanging ideas and fostering innovation in the developing landscape of memory technologies.

Conclusion

Vinod Robert Purayath’s focused dedication to innovation in the field of nonvolatile memory is evident through his extensive patent portfolio and collaborative efforts. His continued work promises to enable more efficient and reliable memory solutions, paving the way for advancements in data storage and technology as a whole.

Profile summary based on public USPTO records.
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