The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2019
Filed:
Apr. 30, 2018
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Vinod Robert Purayath, Cupertino, CA (US);
Nitin K. Ingle, San Jose, CA (US);
Assignee:
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 21/28 (2006.01); H01L 27/11582 (2017.01); H01L 29/06 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 21/28282 (2013.01); H01L 27/11582 (2013.01); H01L 29/0649 (2013.01); H01L 27/1157 (2013.01);
Abstract
In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap 'island.' As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.