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For the Inventor, By the Inventor

Beaverton, OR, United States of America

Vaughn J Grossnickle

This inventor holds 18 USPTO granted patents and 2 published patent applications. Top assignee: Intel Corporation. Active years: 2002-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vaughn J Grossnickle. Retrieved from https://idiyas.com/inventor/vaughn-j-grossnickle

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 66.7

Average Co-Inventor Count = 4.0

ph-index = 4

Forward Citations = 83(Granted Patents)


Location History:

  • Hillsboro, OR (US) (2002 - 2021)
  • Beaverton, OR (US) (2008 - 2022)

Company Filing History:

goldMedal18 out of 56,322 
 
Intel Corporation
 patents

Years Active: 2002-2026

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18 patents (USPTO):Explore Patents
1. 12607656 - Voltage droop detection and frequency recovery (2026-04-21),
2. 11461504 - Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio (2022-10-04),
3. 11211934 - Apparatus to improve lock time of a frequency locked loop (2021-12-28),
4. 11048284 - Self-referenced droop detector circuitry (2021-06-29),
5. 10824764 - Apparatus for autonomous security and functional safety of clock and voltages (2020-11-03),
6. 10790838 - Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop (2020-09-29),
7. 10790832 - Apparatus to improve lock time of a frequency locked loop (2020-09-29),
8. 10614774 - Device, method and system for on-chip generation of a reference clock signal (2020-04-07),
9. 10423182 - Self-referenced droop detector circuitry (2019-09-24),
10. 9876491 - Apparatus, system, and method for re-synthesizing a clock signal (2018-01-23),
11. 9836078 - Clock generation system with dynamic distribution bypass mode (2017-12-05),
12. 9450589 - Clock generation system with dynamic distribution bypass mode (2016-09-20),
13. 9190991 - Apparatus, system, and method for re-synthesizing a clock signal (2015-11-17),
14. 8878579 - System and method for scaling power of a phase-locked loop architecture (2014-11-04),
15. 8756451 - Frequency synthesis methods and systems (2014-06-17),

Title: Innovations of Vaughn J Grossnickle

Introduction

Vaughn J Grossnickle is a notable inventor based in Beaverton, OR (US). He has made significant contributions to the field of technology, holding a total of 18 patents. His work primarily focuses on enhancing the functionality and safety of electronic systems.

Latest Patents

Among his latest innovations is the "Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio." This apparatus is designed to ensure the autonomous security and functional safety (FUSA) of clock signals and voltages. It features a multiplexer that receives an external clock and includes various monitoring circuitries for voltage, duty cycle, frequency degradation, and phase error. Another significant patent is the "Apparatus to improve lock time of a frequency locked loop." This invention comprises a frequency locked loop (FLL) with an oscillator and circuitries that adjust the power supply based on the determined frequency, thereby enhancing performance.

Career Highlights

Vaughn J Grossnickle is currently employed at Intel Corporation, where he continues to innovate and develop advanced technologies. His work at Intel has positioned him as a key player in the field of electronic engineering.

Collaborations

Some of his notable coworkers include Nasser A Kurd and Mark L Neidengard, who have collaborated with him on various projects, contributing to the advancement of technology in their respective fields.

Conclusion

Vaughn J Grossnickle's contributions to technology through his patents and work at Intel Corporation highlight his role as a leading inventor. His innovative solutions continue to impact the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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