The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2017
Filed:
Jul. 15, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Allan Feldman, Portland, OR (US);
Nasser Kurd, Portland, OR (US);
Mark Neidengard, Beaverton, OR (US);
Vaughn Grossnickle, Beaverton, OR (US);
Praveen Mosalikanti, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03K 5/15 (2006.01); G06F 1/04 (2006.01); H03L 7/06 (2006.01); H03L 7/08 (2006.01); H03L 7/083 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); H03K 5/15 (2013.01); H03L 7/06 (2013.01); H03L 7/08 (2013.01); H03L 7/0802 (2013.01); H03L 7/083 (2013.01);
Abstract
In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
Feldman, Allan. (2017). Clock generation system with dynamic distribution bypass mode (U.S. Patent No. 9836078). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9836078
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile