The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Mar. 22, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Praveen Mosalikanti, Portland, OR (US);
Qi Wang, Portland, OR (US);
Mark L. Neidengard, Beaverton, OR (US);
Vaughn J. Grossnickle, Beaverton, OR (US);
Nasser A. Kurd, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); H03L 1/00 (2006.01); H03L 7/099 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H03L 7/08 (2013.01); H03K 3/0315 (2013.01); H03L 1/00 (2013.01); H03L 7/0995 (2013.01); H03B 2201/038 (2013.01);
Abstract
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.