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For the Inventor, By the Inventor

Chiayi, Taiwan

Tzu-Chin Wu

This inventor holds 14 USPTO granted patents and 6 published patent applications. Top assignees: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.. Active years: 2015-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tzu-Chin Wu. Retrieved from https://idiyas.com/inventor/tzu-chin-wu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14 

% Patents Active = 100.0

Average Co-Inventor Count = 4.9

ph-index = 4

Forward Citations = 26(Granted Patents)


Company Filing History:

goldMedal14 out of 7,269 
 
United Microelectronics Corp.
 patents
silverMedal10 out of 354 
 
Fujian Jinhua Integrated Circuit Co., Ltd.
 patents
where one patent can have more than one assignee

Years Active: 2015-2024

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14 patents (USPTO):Explore Patents
1. 12040234 - Semiconductor device and method for fabricating the same (2024-07-16),
2. 10790289 - Method of forming a stop layer filling in a space between spacers (2020-09-29),
3. 10770464 - Semiconductor device including bit line structure of dynamic random access memory (DRAM) and method for fabricating the same (2020-09-08),
4. 10672864 - Manufacturing method of semiconductor memory device (2020-06-02),
5. 10468417 - Semiconductor structure with a conductive line and fabricating method of a stop layer (2019-11-05),
6. 10446559 - Method of fabricating DRAM (2019-10-15),
7. 10332888 - Memory devices and method of manufacturing the same (2019-06-25),
8. 10312080 - Method for forming amorphous silicon multuple layer structure (2019-06-04),
9. 10276650 - Semiconductor memory device and manufacturing method thereof (2019-04-30),
10. 10262895 - Method for forming semiconductor device (2019-04-16),
11. 10249706 - Semiconductor structure (2019-04-02),
12. 9343573 - Method of fabrication transistor with non-uniform stress layer with stress concentrated regions (2016-05-17),
13. 9219151 - Method for manufacturing silicon nitride layer and method for manufacturing semiconductor structure applying the same (2015-12-22),
14. 8937369 - Transistor with non-uniform stress layer with stress concentrated regions (2015-01-20),

Title: Innovator Spotlight: Tzu-Chin Wu, Pioneering Inventor from Chiayi County

Introduction: Tzu-Chin Wu, a visionary inventor hailing from the picturesque Chiayi County, has made a significant impact in the field of semiconductor technology. With an impressive portfolio of 13 patents to his name, Wu's innovative work has revolutionized the memory and semiconductor industries.

Latest Patents: Among Wu's latest patents is his groundbreaking "Method of forming a stop layer filling in a space between spacers," which details a novel technique for fabricating a stop layer in semiconductor devices. Additionally, his patent for a "Semiconductor device including bit line structure of dynamic random access memory (DRAM) and method for fabricating the same" showcases his expertise in optimizing semiconductor manufacturing processes.

Career Highlights: Wu's illustrious career includes stints at renowned companies such as United Microelectronics Corp. and Fujian Jinhua Integrated Circuit Co., Ltd. His contributions have been instrumental in advancing the capabilities of memory technologies, earning him a reputation as a trailblazer in the industry.

Collaborations: Throughout his career, Wu has collaborated with esteemed colleagues such as Chia-Lung Chang and Chih-Chien Liu. Together, they have synergized their collective expertise to drive innovation and push the boundaries of semiconductor design and fabrication.

Conclusion: Tzu-Chin Wu's passion for innovation and relentless pursuit of excellence have cemented his status as a pioneer in the semiconductor industry. His remarkable patents and collaborations underscore his unwavering commitment to advancing technology and shaping the future of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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