The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2024
Filed:
Aug. 03, 2021
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Yi-Fan Li, Tainan, TW;
Po-Ching Su, Tainan, TW;
Yu-Fu Wang, Taoyuan, TW;
Min-Hua Tsai, Tainan, TW;
Ti-Bin Chen, Tainan, TW;
Chih-Chiang Wu, Tainan, TW;
Tzu-Chin Wu, Chiayi County, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 29/4232 (2013.01); H01L 29/78 (2013.01);
Abstract
A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.