Matsumoto, Japan

Tohru Shirakawa

This inventor holds 28 USPTO granted patents, primarily in Semiconductor Devices. Top assignee: Fuji Electric Co., Ltd.. Active years: 2018-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tohru Shirakawa. Retrieved from https://idiyas.com/inventor/tohru-shirakawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 16(Granted Patents)


Location History:

  • Nagano, JP (2018)
  • Matsumoto, JP (2018 - 2024)

Company Filing History:


Years Active: 2018-2025

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Areas of Expertise:
Semiconductor Device
Insulated-Gate Bipolar Transistor
Super Junction MOSFET
Injection Suppression Region
Manufacturing Method
Transistor Characteristics
Reverse-Conducting IGBT
Diode Region
Semiconductor Chip
28 patents (USPTO):Explore Patents

Title: Tohru Shirakawa: Innovator in Semiconductor Technology

Introduction

Tohru Shirakawa is a prominent inventor based in Matsumoto, Japan, known for his substantial contributions to semiconductor technology. With a total of 23 patents to his name, Shirakawa's work focuses on the development and enhancement of semiconductor devices, highlighting his innovative approach to engineering.

Latest Patents

Among Tohru Shirakawa's latest patents is a semiconductor device featuring an insulated gate bipolar transistor (IGBT) structured with a trench-gate configuration. This innovation includes a storage region located directly beneath the p-type base region, utilizing gate trenches and dummy trenches to define the trench-gate structure. The spacing of these trenches, known as the mesa width, is carefully controlled between 0.7 μm and 2 μm. Notably, the design incorporates a gate electrode linked to a gate potential through a first gate insulating film, while a dummy gate electrode serves an emitter potential connected via a second gate insulating film. The inventive arrangement ensures that the total number of gate electrodes constitutes between 60% to 84% of the total number of dummy electrodes.

Another patent involves a sophisticated semiconductor device encompassing both a transistor and a diode portion. This device features an injection suppression region designed to minimize carrier injection of a second conductivity type at the end of the diode portion. The diode component includes a lifetime control region with a lifetime killer, essential for optimizing performance. Each section of the semiconductor substrate is thoughtfully integrated, with the transistor part containing an emitter region and extraction region designed for improved efficiency.

Career Highlights

Shirakawa is currently affiliated with Fuji Electric Co., Ltd., where he leverages his expertise in semiconductor technology to drive innovation. His extensive patent portfolio reflects a commitment to advancing semiconductor devices and their applications in various industries.

Collaborations

In his professional journey, Tohru Shirakawa has collaborated with notable colleagues, including Kaname Mitsuzuka and Yoshiharu Kato. These partnerships foster an environment of shared knowledge and creativity, contributing to the successful development of cutting-edge technologies.

Conclusion

Tohru Shirakawa stands out as a key figure in the realm of semiconductor innovations. His ongoing work at Fuji Electric Co., Ltd. and his impressive collection of patents underscore his dedication to enhancing technology and its capabilities. As advancements in semiconductor devices continue to shape the future, Shirakawa's contributions will undoubtedly play a significant role in the evolution of this critical field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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