The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Dec. 26, 2021
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Daisuke Ozaki, Okaya, JP;

Tohru Shirakawa, Matsumoto, JP;

Yasunori Agata, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0696 (2013.01); H01L 29/0804 (2013.01); H01L 29/1033 (2013.01); H01L 29/1095 (2013.01);
Abstract

Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. The diode portion includes a lifetime control region including a lifetime killer. Both the transistor portion and the diode portion include a base region of a second conductivity type on a surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.


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