Tien Ying Luo

This inventor holds 14 USPTO granted patents and 1 published patent application, primarily in Semiconductor Technology. Top assignees: Freescale Semiconductor,inc., Freescale Semiconductors Inc.. Active years: 2005-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tien Ying Luo. Retrieved from https://idiyas.com/inventor/tien-ying-luo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 14 (Patent Applications = 1)

% Patents Active = 28.6

Average Co-Inventor Count = 3.3

ph-index = 6

Forward Citations = 107(Granted Patents)

Location History:

Beacon, NY (US) (2010)
Austin, TX (US) (2005 - 2014)
Beacon, NV (US) (2016)

Company Filing History:

13 out of 5,491

Freescale Semiconductor,inc.

patents

1 out of 29

Freescale Semiconductors Inc.

patents

Years Active: 2005-2016

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Areas of Expertise:

High-K Oxides

Gate Electrode

Semiconductor Structure

Dielectric Layer

Silicon Nitride

Tensile Stressor

Active Regions

Nanocluster Processing

Oxidation

Nitridation

Diffusion Barrier

Electronic Device

14 patents (USPTO):Sort by Forward CitationsExplore Patents

1. RE45955 - Dual high-K oxides with SiGe channel (2016-03-28),

2. 8659087 - Electronic device with a gate electrode having at least two portions (2014-02-25),

3. 7981808 - Method of forming a gate dielectric by in-situ plasma (2011-07-19),

4. 7829447 - Semiconductor structure pattern formation (2010-11-09),

5. 7767588 - Method for forming a deposited oxide layer (2010-08-03),

6. 7741183 - Method of forming a gate dielectric (2010-06-22),

7. 7700499 - Multilayer silicon nitride deposition for a semiconductor device (2010-04-20),

8. 7678698 - Method of forming a semiconductor device with multiple tensile stressor layers (2010-03-16),

9. 7651935 - Process of forming an electronic device including active regions and gate electrodes of different compositions overlying the active regions (2010-01-26),

10. 7445984 - Method for removing nanoclusters from selected regions (2008-11-04),

11. 7432158 - Method for retaining nanocluster size and electrical characteristics during processing (2008-10-07),

12. 7402472 - Method of making a nitrided gate dielectric (2008-07-22),

13. 7144825 - Multi-layer dielectric containing diffusion barrier material (2006-12-05),

14. 6884685 - Radical oxidation and/or nitridation during metal oxide layer deposition process (2005-04-26),

Title: Tien Ying Luo: Innovator in Semiconductor Technology

Introduction

Tien Ying Luo is a prominent inventor based in Austin, TX, known for his significant contributions to semiconductor technology. With a total of 14 patents to his name, he has made remarkable advancements in the field, particularly in the development of transistor devices.

Latest Patents

Among his latest patents is a method and apparatus for integrating dual gate oxide (DGO) transistor devices and core transistor devices on a single substrate featuring a silicon germanium channel layer. This innovation enhances the performance of PMOS devices by utilizing a dual high-K oxide structure. Another notable patent involves a transistor structure of an electronic device that includes a gate dielectric layer and a gate electrode with a unique surface portion designed to optimize the effective work function in the finished transistor structure.

Career Highlights

Throughout his career, Tien Ying Luo has worked with leading companies in the semiconductor industry, including Freescale Semiconductor, Inc. His expertise in the field has allowed him to contribute to various innovative projects and technologies.

Collaborations

He has collaborated with notable professionals such as Olubunmi O Adetutu and Hsing H Tseng, further enhancing the impact of his work in the semiconductor sector.

Conclusion

Tien Ying Luo's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence advancements in electronic devices and transistor technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: