The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Jul. 25, 2006
Rajesh A. Rao, Austin, TX (US);
Tien Ying Luo, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Robert F. Steimle, Austin, TX (US);
Sherry G. Straub, Pflugerville, TX (US);
Rajesh A. Rao, Austin, TX (US);
Tien Ying Luo, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Robert F. Steimle, Austin, TX (US);
Sherry G. Straub, Pflugerville, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.