The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2016
Filed:
Aug. 05, 2014
Tien Ying Luo, Beacon, NV (US);
Gauri V. Karve, Fishkill, NY (US);
Daniel K. Tekleab, Wappingers Falls, NY (US);
Tien Ying Luo, Beacon, NV (US);
Gauri V. Karve, Fishkill, NY (US);
Daniel K. Tekleab, Wappingers Falls, NY (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices () and core transistor devices () on a single substrate () having a silicon germanium channel layer () in the PMOS device areas (), where each DGO transistor device () includes a metal gate (), an upper gate oxide region () formed from a second, relatively higher high-k metal oxide layer (), and a lower gate oxide region () formed from a first relatively lower high-k layer (), and where each core transistor device () includes a metal gate () and a core gate dielectric layer () formed from only the second, relatively higher high-k metal oxide layer ().