San Jose, CA, United States of America

Suresh Kumar Upadhyayula

This inventor holds 23 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Packaging. Top assignees: Sandisk Technologies Inc., Sandisk Corporation, Micron Technology Incorporated. Active years: 2006-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suresh Kumar Upadhyayula. Retrieved from https://idiyas.com/inventor/suresh-kumar-upadhyayula

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23 

% Patents Active = 95.7

Average Co-Inventor Count = 3.0

ph-index = 6

Forward Citations = 99(Granted Patents)


Location History:

  • San Jose, CA (US) (2006 - 2022)
  • Meridian, ID (US) (2024)

Company Filing History:


Years Active: 2006-2025

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Areas of Expertise:
Semiconductor Device
Microelectronic Devices
Device Packaging
Stacked Die Block
Overheat Prevention
Wire Bonding
USB Device
Leadframe Package
LED Assembly
Electrical Connections
Portable Memory Storage
23 patents (USPTO):Explore Patents

Title: Innovations of Suresh Kumar Upadhyayula in Semiconductor Technology

Introduction

Suresh Kumar Upadhyayula, based in San Jose, California, is an accomplished inventor with a remarkable portfolio of 22 patents. His work primarily focuses on advanced semiconductor technologies, contributing valuable innovations to the field. His latest patents reflect his commitment to enhancing microelectronic device manufacturing processes and packaging techniques.

Latest Patents

One of Upadhyayula's significant contributions is his patent on "Reinforced Semiconductor Device Packaging and Associated Systems and Methods." This innovation introduces a unique packaging method that integrates a substrate with one or more integrated circuit dies, securely coupled via wire bonds. The encapsulant, which encloses the dies and wire bonds, is further enhanced by a reinforcing layer that can be woven from various fibers, such as aramid, carbon, or glass. The packaging process involves positioning a reinforcing textile layer within a mold, alongside the die and substrate, and utilizing a liquid encapsulant that hardens to create a cohesive unit.

Another noteworthy patent is for a "Method of Manufacturing Microelectronic Devices, Related Tools, and Apparatus." This method outlines an efficient process for fabricating microelectronic devices, beginning with forming a wiring layer on a wafer's first surface. It further involves applying laser technology to create modified layers along separation regions, which facilitates the removal of material from the wafer's second surface. By cooling the wafer to a specific temperature, the low dielectric constant layer becomes brittle, allowing for precise separation into individual microelectronic devices.

Career Highlights

Suresh Kumar Upadhyayula has made significant strides in the semiconductor industry, having held notable positions at Sandisk Technologies Inc. and SanDisk Corporation. His expertise has enabled him to play a pivotal role in advancing semiconductor packaging and device manufacturing technologies.

Collaborations

During his career, Upadhyayula has worked alongside esteemed colleagues, including Hem P Takiar and Robert C Miller. Their collaborative efforts have undoubtedly fostered a rich environment for innovation, contributing to the success of their projects and advancements in the semiconductor field.

Conclusion

Suresh Kumar Upadhyayula’s extensive contributions to semiconductor technology through his innovative patents embody the spirit of advancement in microelectronic devices. With a solid foundation in both practical and theoretical aspects of engineering, he continues to influence the industry positively. His work not only signifies progress in device manufacturing but also enhances the reliability and efficiency of semiconductor packaging, ensuring a brighter future for this vital technological sector.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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