The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Feb. 11, 2013
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Suresh Upadhyayula, San Jose, CA (US);

Hem Takiar, Fremont, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 24/06 (2013.01); H01L 25/0657 (2013.01); H01L 24/83 (2013.01); H01L 24/81 (2013.01); H01L 24/86 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4912 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/81205 (2013.01); H01L 2224/81801 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2924/07802 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83 (2013.01); H01L 2224/05554 (2013.01);
Abstract

A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.


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