The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Apr. 01, 2015
Applicant:
Sandisk Technologies Inc., Plano, TX (US);
Inventors:
Chih Chin Liao, Yuanlin Town, TW;
Sung Tan Shih, Taichung, TW;
Suresh Kumar Upadhyayula, San Jose, CA (US);
Ning Ye, San Jose, CA (US);
Assignee:
SANDISK TECHNOLOGIES LLC, Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/49173 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/351 (2013.01);
Abstract
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of pillar bases are formed on the solder mask, and a plurality of solder pillars are applied to the pillar bases. The plurality of solder pillars support one or more semiconductor die above the substrate and the number of solder pillars prevent stresses in the one or more semiconductor die which could otherwise damage the semiconductor die.