The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2017
Filed:
Jan. 09, 2013
Semiconductor device including independent film layer for embedding and/or spacing semiconductor die
Sandisk Semiconductor (Shanghai) Co., Ltd., Shanghai, CN;
Sandisk Information Technology (Shanghai) Co., Ltd., Shanghai, CN;
Ning Ye, San Jose, CA (US);
Chin-Tien Chiu, Taichung, TW;
Suresh Upadhyayula, San Jose, CA (US);
Peng Fu, Kunshan, CN;
Zhong Lu, Shanghai, CN;
Cheeman Yu, Fremont, CA (US);
Yuang Zhang, Shanghai, CN;
Li Wang, Shanghai, CN;
Pradeep Kumar Rai, Shanghai, CN;
Weili Wang, Shanghai, CN;
Enyong Tai, Shanghai, CN;
King Hoo Ong, Shanghai, CN;
Kim Lee Bock, Shanghai, CN;
SanDisk Information Technology (Shanghai) Co., Ltd., Shanghai, CN;
SanDisk Semiconductor (Shanghai) Co. Ltd., Shanghai, CN;
Abstract
A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.