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For the Inventor, By the Inventor

Hsinchu, Taiwan

Sun-Chieh Chien

This inventor holds 73 USPTO granted patents, primarily in Embedded Memory Fabrication (CPC class 4382). Top assignees: United Microelectronics Corp., Micron Electronics, Inc., Other. Active years: 1994-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sun-Chieh Chien. Retrieved from https://idiyas.com/inventor/sun-chieh-chien

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 73

% Patents Active = 94.5

Average Co-Inventor Count = 2.2

ph-index = 14

Forward Citations = 651(Granted Patents)

Forward Citations (Not Self Cited) = 642(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Taipei, TW (1994)
  • Hsin-Chu-City, TW (1995 - 1997)
  • Shiang-Shan Ward, Hsinchu City, TW (1999)
  • Hsin-Chu, TW (1995 - 2014)

Company Filing History:

goldMedal71 out of 7,269 
 
United Microelectronics Corp.
 patents
silverMedal1 out of 432 
 
Micron Electronics, Inc.
 patents
bronzeMedal1 out of 834,453 
Other
 patents

Years Active: 1994-2014

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Areas of Expertise:
Embedded Memory
Dynamic Random Access Memory
Trench-Capacitor
MOS Transistor
Dual Damascene
Contact Plug
Capacitor Fabrication
Chemical Mechanical Polishing
Shallow Trench Isolation
Planarization Method
Low Power SRAM
Fin/HSG DRAM Cell
73 patents (USPTO):Explore Patents
1. 8692359 - Through silicon via structure having protection ring (2014-04-08),
2. 7332392 - Trench-capacitor DRAM device and manufacture method thereof (2008-02-19),
3. 6733597 - Method of cleaning a dual damascene structure (2004-05-11),
4. 6692580 - Method of cleaning a dual damascene structure (2004-02-17),
5. 6635565 - Method of cleaning a dual damascene structure (2003-10-21),
6. 6613655 - Method of fabricating system on chip device (2003-09-02),
7. 6559059 - Method for fabricating a MOS transistor of an embedded memory (2003-05-06),
8. 6509235 - Method for making an embedded memory MOS (2003-01-21),
9. 6509223 - Method for making an embedded memory MOS (2003-01-21),
10. 6509216 - Memory structure with thin film transistor and method for fabricating the same (2003-01-21),
11. 6468919 - Method of making a local interconnect in an embedded memory (2002-10-22),
12. 6468838 - Method for fabricating a MOS transistor of an embedded memory (2002-10-22),
13. 6465364 - Method for fabrication of a contact plug in an embedded memory (2002-10-15),
14. 6461959 - Method of fabrication of a contact plug in an embedded memory (2002-10-08),
15. 6436759 - Method for fabricating a MOS transistor of an embedded memory (2002-08-20),

Title: Sun-Chieh Chien: Pioneering Female Inventor from Hsin-Chu

Introduction: Sun-Chieh Chien is a trailblazing inventor hailing from Hsin-Chu, Taiwan. She has made significant contributions to the field of technology and innovation, particularly in the realm of semiconductor devices.

Latest Patents: Sun-Chieh Chien holds several patents related to semiconductor manufacturing processes and novel electronic components. Her most recent patents focus on enhancing the efficiency and performance of integrated circuits.

Career Highlights: With a background in electrical engineering, Sun-Chieh Chien has had a distinguished career working for leading tech companies in Taiwan. Her expertise in semiconductor design and fabrication has led to groundbreaking advancements in the industry.

Collaborations: Throughout her career, Sun-Chieh Chien has collaborated with top research institutions and universities to further her research in semiconductor technology. Her partnerships have resulted in cutting-edge innovations that have shaped the landscape of modern electronics.

Conclusion: Sun-Chieh Chien's dedication to innovation and her pioneering spirit have solidified her reputation as a respected inventor in the field of semiconductor technology. Her work continues to inspire future generations of inventors and engineers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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