The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
Jan. 19, 2001
Sun-Chieh Chien, Hsin-Chu, TW;
Chien-Li Kuo, Hsin-Chu, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area. Finally, a silicide layer is formed on the top surface of the landing via in the memory array area, as well as on the surfaces of each gate and on the surface of the local interconnect in the periphery circuit area.