Method of fabrication of a contact plug in an embedded memory

Abstract

A semiconductor wafer is provided having both a memory array region and a periphery circuit region. A plurality of gate and LDD are formed in the memory array region. Next, a silicon nitride layer and a second dielectric layer are formed on the surface of the semiconductor wafer, and each contact plug is also formed in the second dielectric layer of the memory array region. The second dielectric layer and the silicon nitride layer in the periphery circuit region are then removed, followed by forming each gate, LDD and spacer in the periphery circuit region by way of a photo-etching-process(PEP), ion implantation, and a deposition process. Finally, a source and drain are formed adjacent to each gate in the periphery circuit region. A self-aligned silicide (salicide) process is performed to form a silicide layer on the surface of each contact plug in the memory array region and on the surface of each gate, source and drain in the periphery circuit region.