logo

For the Inventor, By the Inventor

San Jose, CA, United States of America

Suketu Arun Parikh

LinkedIn

This inventor holds 52 USPTO granted patents and 11 published patent applications, primarily in Semiconductor Processing. Top assignees: Applied Materials, Inc., Solexel, Inc., Spansion LLC.. Active years: 2000-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suketu Arun Parikh. Retrieved from https://idiyas.com/inventor/suketu-arun-parikh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 52 

% Patents Active = 75.0

Average Co-Inventor Count = 2.1

ph-index = 8

Forward Citations = 291(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2000 - 2003)
  • San Jose, CA (US) (2001 - 2024)

Company Filing History:

goldMedal45 out of 14,454 
 
Applied Materials, Inc.
 patents
silverMedal4 out of 64 
 
Solexel, Inc.
 patents
bronzeMedal3 out of 1,075 
 
Spansion LLC.
 patents

Years Active: 2000-2026

Loading Chart...
Areas of Expertise:
Wafer Thinning
Dual Metal Interconnects
Solar Cells
Self-Aligned Via
Metallization Module
3D Interconnects
Atomic Layer Processing
Memory Device Structures
Etch Stop Layers
Transistor Devices
Lithography Applications
52 patents (USPTO):Explore Patents
1. 12660539 - Apparatus for removing etch stop layers (2026-06-16),
2. 12610587 - Backside power rail to deep vias (2026-04-21),
3. 12557343 - Method of ultra thinning of wafer (2026-02-17),
4. 12495582 - Self-aligned wide backside power rail contacts to multiple transistor sources (2025-12-09),
5. 12416080 - Atomic layer self aligned substrate processing and integrated toolset (2025-09-16),
6. 12374584 - Multi color stack for self aligned dual pattern formation for multi purpose device structures (2025-07-29),
7. 12334394 - Methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal (2025-06-17),
8. 12315735 - Methods for removing etch stop layers (2025-05-27),
9. 12183631 - Methods for copper doped hybrid metallization for line and via (2024-12-31),
10. 12148660 - Low resistance and high reliability metallization module (2024-11-19),
11. 12142487 - Methods of modifying portions of layer stacks (2024-11-12),
12. 11948885 - Methods and apparatus for forming dual metal interconnects (2024-04-02),
13. 11749561 - Self-alignment etching of interconnect layers (2023-09-05),
14. 11682668 - Stacked transistor device (2023-06-20),
15. 11658041 - Methods of modifying portions of layer stacks (2023-05-23),

Title: Suketu Arun Parikh: Pioneering Inventor from San Jose

Introduction: Suketu Arun Parikh is a renowned inventor based in San Jose, CA, known for his groundbreaking contributions to various technological fields.

Latest Patents: Suketu Arun Parikh holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his diverse expertise and innovative mindset.

Career Highlights: With a career spanning over two decades, Suketu Arun Parikh has worked with leading tech companies, research institutions, and universities, consistently pushing the boundaries of innovation.

Collaborations: Throughout his career, Suketu Arun Parikh has collaborated with top scientists, engineers, and researchers globally, fostering a culture of creativity and excellence in all his projects.

Conclusion: Suketu Arun Parikh's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…