The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2025
Filed:
Aug. 29, 2022
Applied Materials, Inc., Santa Clara, CA (US);
Suketu Arun Parikh, San Jose, CA (US);
Ashish Pal, San Ramon, CA (US);
El Mehdi Bazizi, San Jose, CA (US);
Andrew Yeoh, Portland, OR (US);
Nitin K. Ingle, San Jose, CA (US);
Arvind Sundarrajan, Singapore, SG;
Guan Huei See, Singapore, SG;
Martinus Maria Berkens, Eindhoven, NL;
Sameer A. Deshpande, Santa Clara, CA (US);
Balasubramanian Pranatharthiharan, San Jose, CA (US);
Yen-Chu Yang, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.