Applied Materials, Inc.

Solexel, Inc.

Spansion Llc.

Suketu Arun Parikh

Mehul B Naik

Mehrdad M Moslehi

Mihaela A Balseanu

Joung Joo Lee

Sanjay S Natarajan

Nitin K Ingle

Roey Shaviv

Pawan Kapur

Michael Anthony Stolfi

Nevran Ozguven

Robin W Cheung

Seshadri Ganguli

Jianshe Tang

Andrew W Yeoh

Somnath S Nag

Rong Tao

David Maxwell Gage

Shirish A Pethe

David Dutton

Tom S Choi

Ning Li

Abhijit Basu Mallick

Srinivas Gandikota

Mark Joseph Saly

Chi-I Lang

Deenesh Padhi

Todd J Egan

Bhaskar Jyoti Bhuyan

Arvind Sundarrajan

Timothy J Thurgate

Girish Anant Dixit

Saravjeet Singh

Abhishek Dube

Benjamin Colombeau

Olov B Karlsson

Yong Cao

Guan Huei See

Arulkumar P Shanmugasundram

Michael D Armacost

Patricia M Liu

Jingmei Liang

Martin Jay Seamons

Jingchun Zhang

Alexander T Schwarm

Christopher S Ngai

Shankar Sinha

Feng Chen

David Xuan-Qi Wang

Daniel Lee Diehl

Nagarajan Rajagopalan

Karl-Josef Kramer

Jothilingam Ramalingam

Jimmy Iskandar

Lu Chen

James M Gee

Tae Won Kim

David Michael Thompson

Matthias Bauer

Sameer Deshpande

Alexander Jansen

Lequn Liu

Tushar Mandrekar

Joe Feng

Tejinder Singh

Jen Shu

Samuel Broydo

Dimitri R Kioussis

Ashish Pal

Charles Gay

H Peter W Hey

Yen-Chu Yang

Aaron Dangerfield

Bradley D Schulze

Roman M Mostovoy

Martinus Maria Berkens

El Mehdi Bazizi

Duncan Harwood

Joe Kramer

Linh Thanh

Meiyee (Maggie Le) Shek

Lifan Yan

Chirantha P Rodrigo

Shuchi Sunil Ojha

Sanjiv Mittal

Hoyung David Hwang

Balasubramanian Pranatharthiharan

Jigar Bhadriklal Patel

Burcu Ucok

Asli Buccu Ucok

Yun Sun

Tsz Keung Cheung

Satya Gowthami Achanta

A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.

Self-aligned wide backside power rail contacts to multiple transistor sources

Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.

Atomic layer self aligned substrate processing and integrated toolset

A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.

Multi color stack for self aligned dual pattern formation for multi purpose device structures

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H) or ammonia (NH) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.

Methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal

Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

Methods for removing etch stop layers

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

Methods for copper doped hybrid metallization for line and via

Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

Low resistance and high reliability metallization module

Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

Methods of modifying portions of layer stacks

Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

Methods and apparatus for forming dual metal interconnects

A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

Self-alignment etching of interconnect layers

Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

Stacked transistor device

Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

Film stack for lithography applications

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Integrated CMOS source drain formation with advanced control

Growing community of inventors

San Jose, CA, United States of America

Suketu Arun Parikh