The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jan. 25, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventor:

Suketu Arun Parikh, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/321 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/02183 (2013.01); H01L 21/32139 (2013.01); H01L 21/762 (2013.01); H01L 23/00 (2013.01); H01L 23/5226 (2013.01);
Abstract

Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.


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