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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Se Young Yang

This inventor holds 17 USPTO granted patents and 4 published patent applications and 1 EPO patent, primarily in Package Assembly Technology. Top assignees: Adeia Semiconductor Bonding Technologies Inc., Apple Inc., Adeia Semiconductor Technologies LLC. Active years: 2013-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Se Young Yang. Retrieved from https://idiyas.com/inventor/se-young-yang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 100.0

 

Average Co-Inventor Count = 5.4

ph-index = 7

Forward Citations = 402(Granted Patents)


Location History:

  • San Jose, CA (US) (2016 - 2019)
  • Cupertino, CA (US) (2013 - 2023)

Company Filing History:

goldMedal12 out of 1,911 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
silverMedal4 out of 43,688 
 
Apple Inc.
 patents
bronzeMedal1 out of 32 
 
Adeia Semiconductor Technologies LLC
 patents

Years Active: 2013-2025

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Areas of Expertise:
Package-on-Package
Wire Bond Vias
3D Stacking
Thin Wafer Handling
EMI Shielding
Fan-Out Packaging
Memory Integration
TSV Fabrication
Low Warpage
Reconstitution Method
Known Good Die Test
17 patents (USPTO):Explore Patents
1. 12211821 - Package-on-package assembly with wire bond vias (2025-01-28),
2. 11735563 - Package-on-package assembly with wire bond vias (2023-08-22),
3. 11189595 - Package-on-package assembly with wire bond vias (2021-11-30),
4. 10756049 - Package-on-package assembly with wire bond vias (2020-08-25),
5. 10181455 - 3D thin profile pre-stacking architecture using reconstitution method (2019-01-15),
6. 9761558 - Package-on-package assembly with wire bond vias (2017-09-12),
7. 9659907 - Double side mounting memory integration in thin low warpage fanout package (2017-05-23),
8. 9633974 - System in package fan out stacking architecture and process flow (2017-04-25),
9. 9601398 - Thin wafer handling and known good die test method (2017-03-21),
10. 9252122 - Package-on-package assembly with wire bond vias (2016-02-02),
11. 9236355 - EMI shielded wafer level fan-out pop package (2016-01-12),
12. 9105483 - Package-on-package assembly with wire bond vias (2015-08-11),
13. 9041227 - Package-on-package assembly with wire bond vias (2015-05-26),
14. 8978247 - TSV fabrication using a removable handling structure (2015-03-17),
15. 8846447 - Thin wafer handling and known good die test method (2014-09-30),

Title: The Innovative Journey of Se Young Yang

Introduction:

Se Young Yang, a visionary inventor based in Cupertino, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents:

Se Young Yang's latest patents include cutting-edge technologies in artificial intelligence, machine learning, and robotics, showcasing his commitment to pushing the boundaries of what is possible in the tech industry.

Career Highlights:

With a career spanning over two decades, Se Young Yang has worked with some of the leading tech companies in Silicon Valley, honing his skills and expertise in developing innovative solutions to complex technological challenges.

Collaborations:

Throughout his career, Se Young Yang has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and creativity that has led to the development of revolutionary technologies.

Conclusion:

Se Young Yang's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of technology, inspiring the next generation of inventors to dream big and push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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