The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

May. 22, 2012
Applicants:

SE Young Yang, Cupertino, CA (US);

Cyprian Emeka Uzoh, San Jose, CA (US);

Michael Huynh, Santa Clara, CA (US);

Rajesh Katkar, San Jose, CA (US);

Inventors:

Se Young Yang, Cupertino, CA (US);

Cyprian Emeka Uzoh, San Jose, CA (US);

Michael Huynh, Santa Clara, CA (US);

Rajesh Katkar, San Jose, CA (US);

Assignee:

Invensas Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/014 (2013.01);
Abstract

A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.


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