Southborough, MA, United States of America

Scott A Kreps

This inventor holds 27 USPTO granted patents and 1 published patent application, plus 2 CIPO patents and 3 EPO patents, primarily in Semiconductor Devices. Top assignees: Rj Mears, LLC, Mears Technologies, Inc., Atomera Incorporated. Active years: 2004-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Scott A Kreps. Retrieved from https://idiyas.com/inventor/scott-a-kreps

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 (Patent Applications = 1)

% Patents Active = 100.0

CIPO Patents = 2

EPO Patents = 3 (Patent Applications = 1)

Average Co-Inventor Count = 2.6

ph-index = 27

Forward Citations = 2,971(Granted Patents)

Location History:

Waltham, MA (US) (2007 - 2009)
Southborough, MA (US) (2004 - 2010)
Indian Harbour Beach, FL (US) (2020)

Company Filing History:

Mears Technologies, Inc.

Years Active: 2004-2020

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Areas of Expertise:

Semiconductor Device

Superlattice

Floating Gate Memory

Strained Superlattice

MOSFET

Band-Engineered

Stress Layer

Dielectric Interface

Semiconductor-On-Insulator

FINFET

Germanium Layer Structure

27 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10741436 - Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface (2020-08-11),

2. 7659539 - Semiconductor device including a floating gate memory cell with a superlattice channel (2010-02-09),

3. 7612366 - Semiconductor device including a strained superlattice layer above a stress layer (2009-11-03),

4. 7598515 - Semiconductor device including a strained superlattice and overlying stress layer and related methods (2009-10-06),

5. 7586116 - Semiconductor device having a semiconductor-on-insulator configuration and a superlattice (2009-09-08),

6. 7531828 - Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions (2009-05-12),

7. 7446002 - Method for making a semiconductor device comprising a superlattice dielectric interface layer (2008-11-04),

8. 7436026 - Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions (2008-10-14),

9. 7435988 - Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel (2008-10-14),

10. 7303948 - Semiconductor device including MOSFET having band-engineered superlattice (2007-12-04),

11. 7288457 - Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions (2007-10-30),

12. 7279701 - Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions (2007-10-09),

13. 7265002 - Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel (2007-09-04),

14. 7202494 - FINFET including a superlattice (2007-04-10),

15. 7153763 - Method for making a semiconductor device including band-engineered superlattice using intermediate annealing (2006-12-26),

Title: Scott A. Kreps: Innovator in Semiconductor Technology

Introduction

Scott A. Kreps, based in Southborough, MA, is a prominent inventor with a notable portfolio that includes 27 patents. His inventive contributions primarily focus on advancements in semiconductor devices, showcasing innovative methodologies and designs that bridge the gap between theoretical concepts and practical applications in electronics.

Latest Patents

Among his latest patents is a groundbreaking method for making a semiconductor device, which incorporates non-monocrystalline stringers adjacent to a superlattice-sti interface. This innovative process involves the formation of spaced apart shallow trench isolation regions in a semiconductor substrate and the creation of a superlattice composed of stacked base semiconductor monolayers, enhancing the overall efficiency of semiconductor devices.

Another significant patent includes a semiconductor device featuring a floating gate memory cell with a superlattice channel. This design integrates a superlattice channel, which enhances the device's performance by employing a combination of stacked base semiconductor monolayers and energy band-modifying layers.

Career Highlights

Throughout his career, Scott has been associated with companies such as R.J. Mears, LLC, and Mears Technologies, Inc. His work in these organizations has been instrumental in developing cutting-edge technologies within the semiconductor field, reinforcing his reputation as a leader in innovation.

Collaborations

Scott Kreps has collaborated with distinguished professionals in the industry, including Robert J. Mears and Marek Hytha. These partnerships have further propelled advancements in semiconductor technologies, establishing a network of skilled innovators dedicated to pushing the boundaries of what is possible.

Conclusion

Scott A. Kreps exemplifies the spirit of innovation in the semiconductor industry, with a robust portfolio of patents and a track record of successful collaborations. His latest inventions reflect a deep understanding of semiconductor technology and a commitment to advancing the field, making him a notable figure among inventors in this critical area of research and development.

Profile summary based on public USPTO records.