The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
May. 25, 2005
Robert J. Mears, Wellesley, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Robert John Stephenson, Newton Upper Falls, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Ilija Dukovski, Newton, MA (US);
Kalipatnam Vivek Rao, Waltham, MA (US);
Samed Halilov, Waltham, MA (US);
Xiangyang Huang, Waltham, MA (US);
Robert J. Mears, Wellesley, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Robert John Stephenson, Newton Upper Falls, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Ilija Dukovski, Newton, MA (US);
Kalipatnam Vivek Rao, Waltham, MA (US);
Samed Halilov, Waltham, MA (US);
Xiangyang Huang, Waltham, MA (US);
MEARS Technologies, Inc., Waltham, MA (US);
Abstract
A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.