For the Inventor, By the Inventor

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Waltham, MA, United States of America

Mears Technologies, Inc.

USPTO Granted Patents = 29

% Expired Patents = 6.9

CIPO Patents = 3

EPO Patents = 3

Trademarks = 2

Forward Citations = 3,207

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14 inventors (with patents filed for the assignee):

Robert J Mears (17 out of 93 patents)

Marek Hytha (10 out of 70 patents)

Jean Augustin Chan Sow Fook Yiptong (10 out of 22 patents)

4. Ilija Dukovski (10 out of 22 patents)

5. Robert John Stephenson (9 out of 41 patents)

6. Scott A Kreps (9 out of 27 patents)

7. Kalipatnam Vivek Rao (8 out of 12 patents)

8. Samed Halilov (8 out of 8 patents)

9. Xiangyang Huang (8 out of 8 patents)

10. Richard A Blanchard (4 out of 271 patents)

11. Erwin Trautmann (1 out of 7 patents)

12. Hideki Takeuchi (1 out of 60 patents)

13. Richard J Jones (1 out of 10 patents)

14. Dale R Setlak (1 out of 96 patents)

15. Adam D Cohen (6 patents)

29 patents: Sort by Forward Citations

1. 9275996 - Vertical semiconductor devices including superlattice punch through stop layer and related methods (2016-03-01),

2. 8389974 - Multiple-wavelength opto-electronic device including a superlattice (2013-03-05),

3. 7928425 - Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods (2011-04-19),

4. 7880161 - Multiple-wavelength opto-electronic device including a superlattice (2011-02-01),

5. 7863066 - Method for making a multiple-wavelength opto-electronic device including a superlattice (2011-01-04),

6. 7812339 - Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures (2010-10-12),

7. 7781827 - Semiconductor device with a vertical MOSFET including a superlattice and related methods (2010-08-24),

8. 7718996 - Semiconductor device comprising a lattice matching layer (2010-05-18),

9. 7700447 - Method for making a semiconductor device comprising a lattice matching layer (2010-04-20),

10. 7659539 - Semiconductor device including a floating gate memory cell with a superlattice channel (2010-02-09),

11. 7625767 - Methods of making spintronic devices with constrained spintronic dopant (2009-12-01),

12. 7612366 - Semiconductor device including a strained superlattice layer above a stress layer (2009-11-03),

13. 7598515 - Semiconductor device including a strained superlattice and overlying stress layer and related methods (2009-10-06),

14. 7586165 - Microelectromechanical systems (MEMS) device including a superlattice (2009-09-08),

15. 7586116 - Semiconductor device having a semiconductor-on-insulator configuration and a superlattice (2009-09-08),

MEARS TECHNOLOGIES, INC. is a leading technology solutions provider established in 2001. With a strong focus on research and development, we offer innovative products and services for various industries. Our expertise includes software development, data analytics, artificial intelligence, cloud computing, and cybersecurity. Visit our website to learn more about our cutting-edge technology solutions and how we can help drive your business forward.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Sep 29 2026

29 Patents

#54 in Waltham, MA

#695 in Massachusetts

#11,606 in US

#22,510 in the World

Waltham, MA, United States of America

Mears Technologies, Inc.

Forward Citations = 3,207

14 inventors:

Robert J Mears (17 out of 93 patents)

Marek Hytha (10 out of 70 patents)

Jean Augustin Chan Sow Fook Yiptong (10 out of 22 patents)

4. Ilija Dukovski (10 out of 22 patents)

5. Robert John Stephenson (9 out of 41 patents)

Please report any incorrect information to [email protected]

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