The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Mar. 16, 2007
Xiangyang Huang, Waltham, MA (US);
Samed Halilov, Waltham, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Ilija Dukovski, Newtonville, MA (US);
Marek Hytha, Brookline, MA (US);
Robert J. Mears, Wellesley, MA (US);
Xiangyang Huang, Waltham, MA (US);
Samed Halilov, Waltham, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Ilija Dukovski, Newtonville, MA (US);
Marek Hytha, Brookline, MA (US);
Robert J. Mears, Wellesley, MA (US);
Mears Technologies, Inc., Waltham, MA (US);
Abstract
A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.