The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Jan. 25, 2005
Robert J. Mears, Wellesley, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Ilija Dukovski, Newton, MA (US);
Robert J. Mears, Wellesley, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Worchester, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Ilija Dukovski, Newton, MA (US);
RJ Mears, LLC, Waltham, MA (US);
Abstract
A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.