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For the Inventor, By the Inventor

San Jose, CA, United States of America

Rajarshi Mukherjee

USPTO Granted Patents = 25

Average Co-Inventor Count = 3.9

ph-index = 8

Forward Citations = 266(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2002 - 2003)
  • Karnataka, IN (2018 - 2020)
  • Mountain View, CA (US) (2022)
  • Bengaluru, IN (2015 - 2023)
  • San Jose, CA (US) (1997 - 2024)

Company Filing History:

goldMedal14 out of 2,493 
 
Synopsys, Inc.
 patents
silverMedal7 out of 39,244 
 
Fujitsu Corporation
 patents
bronzeMedal1 out of 1 
 
Fijutsu Limited
 patent
4. 1 out of 18 
 
Calypto Design Systems, Inc.
 patents
5. 1 out of 2,546 
 
Cadence Design Systems, Inc.
 patents
6. 1 out of 41,012 
 
Apple Inc.
 patents

Years Active: 1997-2025

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25 patents (USPTO):Explore Patents
1. 12393754 - Generating a reduced block model view on-the-fly (2025-08-19),
2. 11907631 - Reset domain crossing detection and simulation (2024-02-20),
3. 11886877 - Memory select register to simplify operand mapping in subroutines (2024-01-30),
4. 11556406 - Automatic root cause analysis of complex static violations by static information repository exploration (2023-01-17),
5. 11467851 - Machine learning (ML)-based static verification for derived hardware-design elements (2022-10-11),
6. 11403450 - Convergence centric coverage for clock domain crossing (CDC) jitter in simulation (2022-08-02),
7. 11288427 - Automated root-cause analysis, visualization, and debugging of static verification results (2022-03-29),
8. 11222154 - State table complexity reduction in a hierarchical verification flow (2022-01-11),
9. 10831961 - Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data (2020-11-10),
10. 10586001 - Automated root-cause analysis, visualization, and debugging of static verification results (2020-03-10),
11. 10460059 - System and method for generating reduced standard delay format files for gate level simulation (2019-10-29),
12. 9886753 - Verification of circuit structures including sub-structure variants (2018-02-06),
13. 9792394 - Accurate glitch detection (2017-10-17),
14. 9529948 - Minimizing crossover paths for functional verification of a circuit description (2016-12-27),
15. 9069699 - Identifying inconsistent constraints (2015-06-30),

Title: The Innovative Journey of Rajarshi Mukherjee

Introduction: Rajarshi Mukherjee, a visionary inventor based in San Jose, CA, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Rajarshi Mukherjee holds several patents in the areas of artificial intelligence, machine learning, and data analytics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Rajarshi Mukherjee has worked for top tech companies in Silicon Valley, where he honed his skills and developed revolutionary solutions.

Collaborations: Throughout his career, Rajarshi Mukherjee has collaborated with leading researchers and engineers to push the boundaries of technological advancements, resulting in impactful inventions that have shaped the industry.

Conclusion: Rajarshi Mukherjee's relentless pursuit of innovation and his passion for creating transformative technologies have solidified his position as a prominent figure in the world of inventors, inspiring the next generation of innovators to push the limits of what is possible.

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