The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
Oct. 05, 2020
Synopsys, Inc., Mountain View, CA (US);
Kaushik De, Pleasanton, CA (US);
Rajarshi Mukherjee, San Jose, CA (US);
David L. Allen, Fremont, CA (US);
Bhaskar Pal, Bangalore, IN;
Sanjay Gulati, New Delhi, IN;
Gaurav Pratap, Noida, IN;
Nishant Patel, Milpitas, CA (US);
Malitha Kulatunga, Colombo, LK;
Sachin Bansal, Noida, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.