Company Filing History:
Years Active: 2022
Title: Gaurav Pratap: Innovator in Hierarchical Verification Flow
Introduction: Gaurav Pratap is a notable inventor based in Noida, India. He has made significant contributions to the field of circuit design and verification. His innovative work focuses on reducing complexity in hierarchical verification flows, which is crucial for efficient circuit design.
Latest Patents: Gaurav Pratap holds a patent titled "State table complexity reduction in a hierarchical verification flow." This patent addresses the challenges of managing power state tables in hierarchical logical block models of circuits. The invention involves identifying peripheral and non-peripheral supplies, merging associated power state tables, and creating a reduced power state table to streamline the verification process.
Career Highlights: Gaurav is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to apply his innovative ideas in practical applications, contributing to advancements in circuit design and verification.
Collaborations: Gaurav has collaborated with talented coworkers, including Kaushik De and Rajarshi Mukherjee. These collaborations have fostered a creative environment that encourages innovation and problem-solving in the field of circuit design.
Conclusion: Gaurav Pratap's contributions to hierarchical verification flow exemplify the importance of innovation in circuit design. His patent and work at Synopsys, Inc. highlight his role as a key player in advancing technology in this field.