The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Dec. 31, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Anshu Malani, Mountain View, CA (US);

Paras Mal Jain, Cupertino, CA (US);

Rajarshi Mukherjee, Mountain View, CA (US);

Sudeep Mondal, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/30 (2020.01); G06F 30/3308 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/3308 (2020.01); G06F 2119/12 (2020.01);
Abstract

A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.


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