The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jan. 30, 2016
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Kaushik De, Pleasanton, CA (US);

Dipti Ranjan Senapati, Nayapalli Bhubaneswar, IN;

Mahantesh D. Narwade, Bangalore, IN;

Namit K. Gupta, San Jose, CA (US);

Rajarshi Mukherjee, San Jose, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/505 (2013.01); G06F 2217/62 (2013.01);
Abstract

Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value. The enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction.


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