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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Peter Cirigliano

This inventor holds 15 USPTO granted patents, primarily in Photoresist Technology. Top assignee: Lam Research Corporation. Active years: 2004-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter Cirigliano. Retrieved from https://idiyas.com/inventor/peter-cirigliano

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 15

% Patents Active = 60.0

Average Co-Inventor Count = 2.8

ph-index = 6

Forward Citations = 115(Granted Patents)


Company Filing History:

goldMedal15 out of 3,958 
 
Lam Research Corporation
 patents

Years Active: 2004-2013

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Areas of Expertise:
Critical Dimension Reduction
Roughness Control
Confinement Ring Assembly
Photoresist Mask Etch
Sidewall Forming Processes
Vertical Profile Fixing
Striation Control
Plasma Stripping
Trench Etch Process
Low-k Dielectrics
Cross-Linking
Patterned Photoresist
15 patents (USPTO):Explore Patents
1. 8614149 - Critical dimension reduction and roughness control (2013-12-24),
2. 8491750 - Adjustable confinement ring assembly (2013-07-23),
3. 8268118 - Critical dimension reduction and roughness control (2012-09-18),
4. 8080168 - Confinement ring drive (2011-12-20),
5. 7910489 - Infinitely selective photoresist mask etch (2011-03-22),
6. 7772122 - Sidewall forming processes (2010-08-10),
7. 7695632 - Critical dimension reduction and roughness control (2010-04-13),
8. 7682516 - Vertical profile fixing (2010-03-23),
9. 7491647 - Etch with striation control (2009-02-17),
10. 7396769 - Method for stripping photoresist from etched wafer (2008-07-08),
11. 7364623 - Confinement ring drive (2008-04-29),
12. 7294580 - Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition (2007-11-13),
13. 6909195 - Trench etch process for low-k dielectrics (2005-06-21),
14. 6794293 - Trench etch process for low-k dielectrics (2004-09-21),
15. 6780569 - Post-development treatment of patterned photoresist to promote cross-linking of polymer chains (2004-08-24),

Title: Peter Cirigliano: Innovator in Semiconductor Technology

Introduction

Peter Cirigliano is a prominent inventor based in Sunnyvale, CA, known for his significant contributions to semiconductor technology. With a total of 15 patents to his name, Cirigliano has made a remarkable impact in the field of semiconductor processing.

Latest Patents

Among his latest patents, Cirigliano has developed a method for critical dimension reduction and roughness control. This innovative method involves forming a feature in an etch layer by creating a photoresist layer that is patterned to form features with specific sidewalls. A control layer is then formed over the photoresist layer, allowing for precise etching into the etch layer using different chemistries. Another notable patent is the adjustable confinement ring assembly, which enhances plasma confinement in semiconductor processing chambers. This assembly includes multiple confinement rings that can be adjusted to optimize the processing environment.

Career Highlights

Cirigliano has built a successful career at Lam Research Corporation, where he has been instrumental in advancing semiconductor manufacturing technologies. His work has not only contributed to the efficiency of semiconductor processes but has also paved the way for innovations in the industry.

Collaborations

Throughout his career, Cirigliano has collaborated with talented individuals such as S M Reza Sadjadi and Sangheon Lee. These collaborations have fostered a creative environment that has led to groundbreaking advancements in semiconductor technology.

Conclusion

Peter Cirigliano's contributions to the semiconductor industry through his innovative patents and collaborative efforts highlight his role as a key figure in advancing technology. His work continues to influence the field and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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