Lam Research Corporation

Peter Cirigliano

S M Reza Sadjadi

Eric A Hudson

Sangheon Lee

Zhisong Huang

Jisoo Kim

Robert Charatan

Ji Soo Kim

Sean S Kang

Reza Sadjadi

David R Pirkle

Vinay Pohray

Dae-Han Choi

SiYi Li

Steve Lassig

Peter K Loewenhardt

Douglas L Keil

Mark Henry Wilcoxson

James V Tietz

Ji Zhu

Helen H Zhu

Seokmin Yun

Wan-Lin Chen

Daxing Ren

Thomas S Choi

Dongho Heo

Daehan Choi

Sm Reza Sadjadi

Dae-han Choi

A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Critical dimension reduction and roughness control

A plasma confinement assembly for a semiconductor processing chamber is provided. The assembly includes a plurality of confinement rings disposed over each other, and each of the plurality of confinement rings is separated by a space. A plunger moveable in a plane substantially orthogonal to the confinement rings. A proportional adjustment support is provided and coupled to the plunger. The proportional adjustment support is configured to move the confinement rings to one or more positions, such that the plunger is settable in positions along the plane. The positions define the space separating confinement rings, and the space is proportionally set between the confinement rings. The proportional adjustment support is defined by a plurality of support legs, and each of the support legs is pivotably interconnected with at least one other support leg.

Adjustable confinement ring assembly

A confinement assembly for a semiconductor processing chamber is provided. The confinement assembly includes a plurality of confinement rings disposed over each other. Each of the plurality of confinement rings are separated by a space and each of the plurality of confinement rings have a plurality of holes defined therein. A plunger extending through aligned holes of corresponding confinement rings is provided. The plunger is moveable in a plane substantially orthogonal to the confinement rings. A proportional adjustment support is affixed to the plunger. The proportional adjustment support is configured to support the confinement rings, such that as the plunger moves in the plane, the space separating each of the plurality of confinement rings is proportionally adjusted. In one embodiment the proportional adjustment support is a bellows sleeve. A semiconductor processing chamber and a method for confining a plasma in an etch chamber having a plurality of confinement rings are provided.

Confinement ring drive

A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.

Infinitely selective photoresist mask etch

An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.

Sidewall forming processes

A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have irregular profiles along depths of the photoresist features. The irregular profiles along the depths of the photoresist features of the sidewalls of the photoresist features are corrected comprising at least one cycle, where each cycle comprises a sidewall deposition phase and a profile shaping phase. Feature is etched into the etch layer through the photoresist features. The mask is removed.

Vertical profile fixing

A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Etch with striation control

A method of forming a feature in a low-k (k&#x3c;3.0) dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A stripping gas comprising COis provided. A plasma is formed from the stripping gas comprising CO. The plasma from the stripping gas comprising COis used to strip the patterned photoresist mask.

Method for stripping photoresist from etched wafer

A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.

Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition

The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Trench etch process for low-k dielectrics

A method for creating semiconductor devices is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. Polymers in the patterned photoresist layer are chemically cross-linked by exposure to at least one reactive chemical. The pattern in the photoresist layer is transferred to the wafer. A reaction chamber for processing a wafer with a patterned layer of photoresist material, wherein the photoresist material was patterned by exposing the photoresist material using light of a wavelength less than 248 nm is provided. A chamber is provided with a central cavity. A wafer support for supporting the wafer in the central cavity is provided. A cross-linking reactive chemical source in fluid contact with the chamber and which provides a reactive chemical which causes cross-linking of the photoresist is provided.

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Sunnyvale, CA, United States of America

Peter Cirigliano