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For the Inventor, By the Inventor

Tokyo, Japan

Noriaki Fujiki

This inventor holds 13 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 1994-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Noriaki Fujiki. Retrieved from https://idiyas.com/inventor/noriaki-fujiki

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 13

% Patents Active = 84.6

Average Co-Inventor Count = 3.1

ph-index = 6

Forward Citations = 177(Granted Patents)


Location History:

  • Itami, JP (2001)
  • Hyogo, JP (1994 - 2002)
  • Tokyo, JP (2003 - 2008)

Company Filing History:

goldMedal8 out of 21,351 
 
Mitsubishi Denki Kabushiki Kaisha
 patents
silverMedal5 out of 3,781 
 
Renesas Technology Corp.
 patents

Years Active: 1994-2008

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13 patents (USPTO):Explore Patents
1. 7423301 - Semiconductor device including fuse elements and bonding pad (2008-09-09),
2. 7335537 - Method of manufacturing semiconductor device including bonding pad and fuse elements (2008-02-26),
3. 7217965 - Semiconductor device including fuse elements and bonding pad (2007-05-15),
4. 6888258 - Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same (2005-05-03),
5. 6677682 - Multilayer interconnection structure including an alignment mark (2004-01-13),
6. 6586838 - Semiconductor device (2003-07-01),
7. 6339257 - Semiconductor device (2002-01-15),
8. 6283835 - Method and apparatus for manufacturing a semiconductor integrated circuit (2001-09-04),
9. 6178972 - Method and apparatus for manufacturing a semiconductor integrated circuit (2001-01-30),
10. 5736791 - Semiconductor device and bonding pad structure therefor (1998-04-07),
11. 5510653 - Semiconductor device including silicon ladder resin layer (1996-04-23),
12. 5488014 - Interconnection structure of semiconductor integrated circuit device and (1996-01-30),
13. 5313101 - Interconnection structure of semiconductor integrated circuit device (1994-05-17),

Title: Noriaki Fujiki: Innovator in Semiconductor Technology

Introduction

Noriaki Fujiki is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His work focuses on innovative semiconductor devices and manufacturing methods that enhance performance and reliability.

Latest Patents

Fujiki's latest patents include a semiconductor device that features fuse elements and a bonding pad. This device comprises a lower-layer substrate, a fuse positioned above it, and a silicon oxide film that covers the fuse and part of the substrate. Notably, the silicon oxide film is thicker than the fuse, with an opening opposite the fuse. Another significant patent details a method for manufacturing a semiconductor device that includes bonding pads and fuse elements. This method involves forming insulating films, etching aluminum layers to create bonding pads and fuse elements, and utilizing plasma chemical vapor deposition for additional insulating layers.

Career Highlights

Throughout his career, Noriaki Fujiki has worked with notable companies such as Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

Fujiki has collaborated with esteemed colleagues, including Takashi Yamashita and Shigeru Harada. Their combined expertise has contributed to advancements in the semiconductor field.

Conclusion

Noriaki Fujiki's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the development of advanced semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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