Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Noriaki Fujiki

Takashi Yamashita

Shigeru Harada

Junko Izumitani

Hiroki Takewaka

Takeru Matsuoka

Junichi Arima

Tsutomu Tanaka

Hiroshi Adachi

Etsushi Adachi

Kazunobu Miki

A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

Semiconductor device including fuse elements and bonding pad

A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Method of manufacturing semiconductor device including bonding pad and fuse elements

A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.

Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same

An interlayer insulating film ( ) is formed on a substrate ( ), and a polysilicon layer ( ) is formed on the interlayer insulating film ( ). An interlayer insulating film ( ) is formed to cover the polysilicon layer ( ), and a polysilicon layer ( ) is formed on the interlayer insulating film ( ). An interlayer insulating film ( ) is formed to cover the interlayer insulating film ( ). A hole ( M) for a mark to constitute an alignment mark or the like is formed from a surface ( S) of the interlayer insulating film ( ) to the polysilicon layer ( ). The hole ( M) for a mark is larger than a contact hole formed from the surface ( S) to the substrate ( ) but is shallower than the contact hole. Consequently, a concave portion corresponding to the hole ( M) for a mark is formed, with difficulty, on a silicon oxide layer to be subjected to CMP polishing and then become an interlayer insulting film ( ). Therefore, it is possible to prevent a slurry from remaining in the concave portion. Thus, it is possible to obtain a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattering of the slurry to be used for a CMP method.

Multilayer interconnection structure including an alignment mark

To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH -based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH -based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH -based silicon oxide film. The SiH -based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.

Semiconductor device

A semiconductor device which is provided with enhanced reliability and capable of preventing cracking of a layer below an interconnection layer and separation of the interconnection layer and a bonding pad electrode layer. The semiconductor device includes: an interconnection layer including a conductive material formed on a silicon substrate; an intermediate layer formed in contact with interconnection layer and including a titanium layer and a titanium nitride layer; and a bonding pad electrode layer which is in contact with the intermediate layer.

A method and an apparatus for manufacturing a semiconductor integrated circuit in which semiconductor elements (,) and a wiring structure connecting the semiconductor elements (,) one another are located on a semiconductor substrate (,). In the method or apparatus, a series of wiring elements (,), each of which constructs the wiring structure is formed sequentially, then the semiconductor integrated circuit under manufacturing process is washed by neutral solution containing oxidant during the process of forming of the wiring elements (,).

Method and apparatus for manufacturing a semiconductor integrated circuit

In a semiconductor device having a bonding pad structure of a multilayered wiring structure comprising a first wiring layer and a second wiring layers which is located over the first wiring layer and an interlayer insulation layer between the wiring layers which has an electrically conductive component so as to electrically connect the wiring layers, the bonding pad structure is such that no crack is formed in the interlayer insulation layer during wire bonding. The bonding pad structure is so arranged that an area of the first wiring layer area is smaller than that of the second wiring layer or the first wiring layer is formed outside a bonding region of the second wiring layer under the second wiring layer.

Semiconductor device and bonding pad structure therefor

Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.

Semiconductor device including silicon ladder resin layer

A surface of a first aluminum interconnection layer in a connection hole is exposed to a plasma of oxygen or fluorine-containing gas during the forming step of the connection hole. In order to remove the thin deterioration layer which forms as a result, sputter etching is effected by an argon ion. There are residual particles of the oxide and fluoride of aluminum on the surface of the first aluminum interconnection layer. A titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum layer through the through hole. A titanium compound layer is formed on the titanium layer. A second aluminum layer is formed on the titanium compound layer. A heat treatment is effected to decompose the residual particles and to form an intermetallic compound (TiAl.sub.3).

Interconnection structure of semiconductor integrated circuit device and

A semiconductor integrated circuit device has an interconnection structure in which multilayer aluminum interconnection layers are connected through a connection hole. A first aluminum interconnection layer is formed on a main surface of said semiconductor substrate. An insulating layer is formed on the first aluminum interconnection layer and has a through hole extending to a surface of the first aluminum interconnection layer. A second aluminum interconnection layer is formed on the insulating layer and is electrically connected to the first aluminum interconnection layer through the through hole. The second aluminum interconnection layer includes a titanium layer, a titanium nitride layer and an aluminum alloy layer. The titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum interconnection layer through the through hole. The titanium nitride layer is formed on the titanium layer. The aluminum alloy layer is formed on the titanium nitride layer. An electrical contact resistance between the first and second aluminum interconnection layers is stabilized, and resistance against the electron-migration and stress-migration is improved in the interconnection structure.

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Tokyo, Japan

Noriaki Fujiki