The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 1996

Filed:

Mar. 31, 1993
Applicant:
Inventors:

Noriaki Fujiki, Hyogo, JP;

Shigeru Harada, Hyogo, JP;

Hiroshi Adachi, Hyogo, JP;

Etsushi Adachi, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257759 ; 257638 ; 257760 ;
Abstract

Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.


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