Multilayer interconnection structure including an alignment mark

Abstract

An interlayer insulating film ( ) is formed on a substrate ( ), and a polysilicon layer ( ) is formed on the interlayer insulating film ( ). An interlayer insulating film ( ) is formed to cover the polysilicon layer ( ), and a polysilicon layer ( ) is formed on the interlayer insulating film ( ). An interlayer insulating film ( ) is formed to cover the interlayer insulating film ( ). A hole ( M) for a mark to constitute an alignment mark or the like is formed from a surface ( S) of the interlayer insulating film ( ) to the polysilicon layer ( ). The hole ( M) for a mark is larger than a contact hole formed from the surface ( S) to the substrate ( ) but is shallower than the contact hole. Consequently, a concave portion corresponding to the hole ( M) for a mark is formed, with difficulty, on a silicon oxide layer to be subjected to CMP polishing and then become an interlayer insulting film ( ). Therefore, it is possible to prevent a slurry from remaining in the concave portion. Thus, it is possible to obtain a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattering of the slurry to be used for a CMP method.