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For the Inventor, By the Inventor

Taichung, Taiwan

Nien-Yu Tsai

This inventor holds 15 USPTO granted patents. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Promos Technologies, Inc, Macronix International Co., Ltd.. Active years: 2002-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nien-Yu Tsai. Retrieved from https://idiyas.com/inventor/nien-yu-tsai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 100.0

Average Co-Inventor Count = 3.2

ph-index = 3

Forward Citations = 24(Granted Patents)


Location History:

  • Taipei, TW (2002 - 2006)
  • Hsinchu, TW (2003 - 2023)
  • Taichung, TW (2015 - 2023)

Company Filing History:

goldMedal10 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal4 out of 358 
 
Promos Technologies, Inc
 patents
bronzeMedal1 out of 3,609 
 
Macronix International Co., Ltd.
 patents

Years Active: 2002-2023

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15 patents (USPTO):Explore Patents
1. 11714946 - Standard cell and semiconductor device including anchor nodes and method of making (2023-08-01),
2. 11681850 - Multi-patterning graph reduction and checking flow method (2023-06-20),
3. 11106852 - Standard cell and semiconductor device including anchor nodes and method of making (2021-08-31),
4. 11017148 - Multi-patterning graph reduction and checking flow method (2021-05-25),
5. 10713407 - Standard cell and semiconductor device including anchor nodes (2020-07-14),
6. 10430544 - Multi-patterning graph reduction and checking flow method (2019-10-01),
7. 10162928 - Method of designing a semiconductor device, system for implementing the method and standard cell (2018-12-25),
8. 10121694 - Methods of manufacturing a semiconductor device (2018-11-06),
9. 9514266 - Method and system of determining colorability of a layout (2016-12-06),
10. 9038010 - DRC format for stacked CMOS design (2015-05-19),
11. 8895447 - Semiconductor hole structure (2014-11-25),
12. 6998277 - Method of planarizing spin-on material layer and manufacturing photoresist layer (2006-02-14),
13. 6743726 - Method for etching a trench through an anti-reflective coating (2004-06-01),
14. 6514817 - Method of forming shallow trench (2003-02-04),
15. 6410417 - Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer (2002-06-25),

Title: Nien-Yu Tsai: Innovator in Semiconductor Technology

Introduction

Nien-Yu Tsai is a prominent inventor based in Taichung, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work focuses on enhancing the functionality and efficiency of semiconductor devices.

Latest Patents

Among his latest patents is a groundbreaking invention titled "Standard cell and semiconductor device including anchor nodes and method of making." This patent describes a semiconductor device that features a first cell with a functional feature and anchor nodes, which are crucial for its operational integrity. Another notable patent is the "Multi-patterning graph reduction and checking flow method," which outlines a method for generating photomasks through a circuit graph, improving the efficiency of semiconductor manufacturing processes.

Career Highlights

Nien-Yu Tsai has worked with leading companies in the semiconductor industry, including Taiwan Semiconductor Manufacturing Company Ltd. and Promos Technologies, Inc. His experience in these organizations has allowed him to develop innovative solutions that address complex challenges in semiconductor design and production.

Collaborations

Throughout his career, Nien-Yu has collaborated with talented individuals such as Wen-Ju Preet Yang and Chin-Chang Hsu. These partnerships have fostered a creative environment that has led to the development of advanced technologies in the semiconductor field.

Conclusion

Nien-Yu Tsai's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the future of semiconductor devices and manufacturing processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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