The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Oct. 21, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Jung Chang, Zhubei, TW;

Chin-Chang Hsu, Banqiao, TW;

Ying-Yu Shen, Chiayi, TW;

Nien-Yu Tsai, Taichung, TW;

Wen-Ju Yang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); G06F 17/50 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); H01L 23/528 (2013.01); H01L 23/5222 (2013.01); H01L 23/53295 (2013.01); H01L 2224/13 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (DRC) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps.


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