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For the Inventor, By the Inventor

Changhua, Taiwan

Mu-Tsang Lin

This inventor holds 41 USPTO granted patents and 1 published patent application, primarily in Semiconductor Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2002-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mu-Tsang Lin. Retrieved from https://idiyas.com/inventor/mu-tsang-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 41 

% Patents Active = 75.6

Average Co-Inventor Count = 4.0

ph-index = 5

Forward Citations = 105(Granted Patents)


Location History:

  • Hsin-Chu, TW (2002)
  • Ho-May, TW (2003)
  • Chung-hua, TW (2004)
  • Zhwengwei, TW (2005)
  • Changhua, TW (2004 - 2006)
  • Hemei Township, Changhua County, TW (2007 - 2018)
  • Changhua County, TW (2017 - 2023)
  • Hemei Township, TW (2017 - 2023)

Company Filing History:

goldMedal41 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2002-2026

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Areas of Expertise:
FinFET
Semiconductor Device
Gate Stack
Doped Gate Spacer
Humidity Control
Shallow Trench Isolation
Epitaxy Structure
Field Effect Transistor
Wafer Transfer
Contamination Reduction
Temperature Sensing
Statistical Process Control
41 patents (USPTO):Explore Patents
1. 12615995 - Interface tool (2026-04-28),
2. 11854851 - Interface tool (2023-12-26),
3. 11723152 - Oxygen and humidity control in storage device (2023-08-08),
4. 11721746 - Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features (2023-08-08),
5. 11631748 - Structure and formation method of semiconductor device structure with gate stack (2023-04-18),
6. 11594534 - Semiconductor device and manufacturing method thereof (2023-02-28),
7. 11342458 - Semiconductor structure and fabricating method thereof (2022-05-24),
8. 11018259 - Semiconductor device comprising gate structure and doped gate spacer (2021-05-25),
9. 11004845 - Semiconductor device and manufacturing method thereof (2021-05-11),
10. 10879399 - Method of manufacturing semiconductor device comprising doped gate spacer (2020-12-29),
11. 10818794 - Semiconductor structure and fabricating method thereof (2020-10-27),
12. 10811516 - Structure and formation method of semiconductor device structure with gate stack (2020-10-20),
13. 10770569 - Semiconductor device (2020-09-08),
14. 10749014 - Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features (2020-08-18),
15. 10636788 - Semiconductor device and manufacturing method thereof (2020-04-28),

Title: The Innovative Journey of Mu-Tsang Lin

Introduction: Mu-Tsang Lin, a pioneering inventor hailing from Changhua County, Taiwan, has made significant contributions to the field of technology with her groundbreaking inventions.

Latest Patents: Mu-Tsang Lin's latest patents include a revolutionary smart home device that integrates artificial intelligence for enhanced security and convenience, as well as a sustainable energy solution that harnesses solar power for rural communities.

Career Highlights: With over two decades of experience in the tech industry, Mu-Tsang Lin has a proven track record of developing cutting-edge solutions. She has received multiple awards for her innovative work, including the prestigious Inventor of the Year accolade.

Collaborations: Mu-Tsang Lin has collaborated with leading research institutions and universities to further advance her inventions. Her partnerships have led to the development of patented technologies that have positively impacted various sectors.

Conclusion: Mu-Tsang Lin's dedication to innovation and her passion for creating solutions that address real-world challenges have solidified her reputation as a trailblazing inventor in the tech industry. Her relentless pursuit of excellence continues to inspire future generations of inventors worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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