Taiwan Semiconductor Manufacturing Comp. Ltd.

Mu-Tsang Lin

Tung-Wen Cheng

Che-Cheng Chang

Chang-Yin Chen

Shih-Hao Chen

Wei-Yang Lo

Zhe-Hao Zhang

Chih-Han Lin

Bo-Feng Young

Jr-Jung Lin

Chih-Shan Chen

Yung Jung Chang

Jian-Hong Chen

Chia-Ling Chan

Jyh-Shiou Hsu

Kuo Hui Chang

Tien-Wen Wang

Chon-Hwa Chu

Ie-Fun Lai

Wen-Sheng Chien

Chyi-Tsong Ni

Yung-Jung Chang

Su-Horng Lin

Chia-Hung Chung

Pin-Yi Hsin

Cheng-Yen Yu

Yu-Lun Lin

Yu-Yi Wu

Jui Fu Hseih

Pu Kuan Fang

Shen-Min Yang

Sen-Tay Chang

Chin-Chih Chen

Kong-Hsin Teng

Jen-Hom Chen

Wie-Liang Tsai

Cherng-Chang Lee

Yen-Chan Lee

Chia-Hsin Liu

Tung-Mao Lee

Zhih-Lu Juang

Yao-Ping Yang

Tse-Lun Chang

Jung-Wang Lu

Yao-Fey Chuang

Yi-Yu Wu

Joseph W L Fang

Yao-Wen Wu

A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.

Interface tool

A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features

The present disclosure describes a storage device including a top panel, a bottom panel, a back panel, a front panel, and two side panels configured to form an enclosed volume. The storage device further includes multiple slots disposed at inner surfaces of the two side panels and configured to hold a substrate, a gas diffuser disposed at an inner surface of the back panel and configured to provide a purge gas to the enclosed volume, an isolation gas device disposed on an inner surface of the top panel and adjacent to a top portion of the front panel, and an isolation gas line configured to connect the isolation gas device to the gas diffuser. The isolation gas device is configured to inject the purge gas into a front portion of the storage device and in a direction from the top panel toward the bottom panel.

Oxygen and humidity control in storage device

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Structure and formation method of semiconductor device structure with gate stack

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

Semiconductor device and manufacturing method thereof

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Semiconductor structure and fabricating method thereof

A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

Semiconductor device comprising gate structure and doped gate spacer

Method of manufacturing semiconductor device comprising doped gate spacer

A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure.

Semiconductor device

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer. The semiconductor device further includes a second dielectric layer vertically between the first dielectric layer and the gate spacer, wherein the first and second dielectric layers include different materials, and wherein the second dielectric layer is in physical contact with the gate spacer and the first dielectric layer.

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Changhua County, Taiwan

Mu-Tsang Lin