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For the Inventor, By the Inventor

Milpitas, CA, United States of America

Michael E Thomas

USPTO Granted Patents = 55

Average Co-Inventor Count = 1.6

ph-index = 22

Forward Citations = 1,501(Granted Patents)

Forward Citations (Not Self Cited) = 1,486(Oct 12, 2025)


Inventors with similar research interests:


Location History:

  • Cupertino, CA (US) (1984 - 1995)
  • Winston-Salem, NC (US) (1996)
  • Fremont, CA (US) (2000)
  • Milpitas, CA (US) (1991 - 2013)

Company Filing History:

goldMedal38 out of 4,791 
 
National Semiconductor Corporation
 patents
silverMedal5 out of 335 
 
Fairchild Camera and Instrument Corp.
 patents
bronzeMedal4 out of 1,302 
 
Fairchild Semiconductor Corporation
 patents
4. 4 out of 15,586 
 
Honeywell International Inc.
 patents
5. 2 out of 993 
 
Novellus Systems Incorporated
 patents
6. 1 out of 2,921 
 
Dow Corning Corporation
 patents
7. 4 out of 832,680 
Other
 patents
where one patent can have more than one assignee

Years Active: 1984-2013

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55 patents (USPTO):Explore Patents
1. 8440388 - Method to restore hydrophobicity in dielectric films and materials (2013-05-14),
2. 7915181 - Repair and restoration of damaged dielectric materials and films (2011-03-29),
3. 7858294 - Method to restore hydrophobicity in dielectric films and materials (2010-12-28),
4. 7029826 - Method to restore hydrophobicity in dielectric films and materials (2006-04-18),
5. 6593615 - Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD (2003-07-15),
6. 6590265 - Semiconductor device with sidewall spacers having minimized area contacts (2003-07-08),
7. 6548323 - Method of preparing light-sensitive integrated circuits for packaging (2003-04-15),
8. 6509283 - Thermal oxidation method utilizing atomic oxygen to reduce dangling bonds in silicon dioxide grown on silicon (2003-01-21),
9. 6383933 - Method of using organic material to enhance STI planarization or other planarization processes (2002-05-07),
10. 6348421 - Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD (2002-02-19),
11. 6277726 - Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects (2001-08-21),
12. 6242354 - Semiconductor device with self aligned contacts having integrated silicide stringer removal and method thereof (2001-06-05),
13. 6103629 - Self-aligned interconnect using high selectivity metal pillars and a via (2000-08-15),
14. 6099639 - Method for solid-state formation of diamond (2000-08-08),
15. 6074929 - Box isolation technique for integrated circuit structures (2000-06-13),

Title: The Inventor Profile of Michael E Thomas

Introduction: Michael E Thomas is a renowned inventor based in Milpitas, CA (US) known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Michael E Thomas holds several patents in the areas of electronics, software, and telecommunications, showcasing his expertise and creativity in developing cutting-edge solutions.

Career Highlights: With over two decades of experience in the industry, Michael E Thomas has worked for leading tech companies, where he has spearheaded numerous projects that have revolutionized the way we interact with technology on a daily basis.

Collaborations: Throughout his career, Michael E Thomas has collaborated with top engineers, designers, and researchers to bring his ideas to life, resulting in successful products that have had a significant impact on the market.

Conclusion: Michael E Thomas continues to be a driving force in the world of innovation, constantly pushing the boundaries of what is possible and inspiring the next generation of inventors to think outside the box.

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