National Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Other

Honeywell International Inc.

Fairchild Semiconductor Corporation

Novellus Systems Incorporated

Dow Corning Corporation

Michael E Thomas

Irfan Abdulqayyum Saadat

Jeffrey D Chinn

Nigel P Hacker

James S Drage

Jen Shu

Ashok K Kapoor

Madhukar B Vora

Eliot K Broadbent

Vassili M Kitch

Wojciech P Maly

Everhardus P Van De Van

James Montague Cleeves

Victor Y Lu

Jeffrey Robert Perry

Robert Charles Camilletti

Reda R Razouk

John M Pierce

Hemraj K Hingarh

Anil Shriram Bhanap

Ananth Naman

Brian J Daniels

Wenya Fan

Ronald P Kovacs

De-Ling Zhou

Lei Jin

Euisik Yoon

Michael A Glenn

Kranti V Anand

Aaron Grant Simmons

Robert L Brown

Thomas Keyser

Kranti V Anand, Deceased

Tiffany Nguyen

Richard Von Salza Brown

Satoshi Sekigahama

Robert A Sabsowitz

Prochy Sethna

Robert Brown

Andres D Asuncion

Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.

Method to restore hydrophobicity in dielectric films and materials

Methods of repairing voids in a material are described herein that include: a) providing a material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c) chemically capping at least some of the plurality of reactive silanol groups with the at least one of the reactive surface modification agents. Methods of carbon restoration in a material are also described that include: a) providing a carbon-deficient material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c)chemically capping at least some of the plurality of reactive silanol groups with the at least one of the reactive surface modification agents. In addition, methods are described herein for reducing the condensation of a film and/or a carbon-deficient film that include: a) providing a film having a plurality of reactive silanol groups; b) placing the film into a plasma chamber; c) introducing a plurality of reactive organic moieties-containing silanes into the chamber; and d) allowing the silanes to react with at least some of the reactive silanol groups. Dielectric materials and low-k dielectric materials are described herein that comprise: a) an inorganic material having a plurality of silicon atoms; and b) a plurality of organic moiety-containing silane compounds, wherein the silane compounds are coupled to the inorganic material through at least some of the silicon atoms.

Repair and restoration of damaged dielectric materials and films

Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD

A contact opening ( ) is provided in a dielectric layer ( ) overlaying a gate electrode ( ). The contact opening and gate electrode are of substantially the same width, thus allowing for minimized area contact. A pair of process buffering regions ( ) situated along the sidewalls of the gate electrode furnish additional landing area for the contact opening without exposing the sidewalls of the gate electrode.

Semiconductor device with sidewall spacers having minimized area contacts

A process for preparing a light-sensitive integrated circuit (IC) for packaging that provides a reduced exposure of the light-sensitive IC to light. The process includes providing a semiconductor substrate (e.g., a silicon wafer) with a plurality of light-sensitive ICs formed in/on its upper surface. The lower surface is optionally coated with opaque material. Next, the semiconductor substrate is diced to form individual light-sensitive ICs, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges. The semiconductor substrate lateral edges (and optionally backside) are then spray coated with an opaque material (e.g., opaque ink) to form an opaque layer covering the semiconductor substrate lateral edges. The opaque layer prevents light from entering the semiconductor substrate through the lateral edges and interfering with the operation of the light-sensitive IC. The inventive process is simple and inexpensive, employing, for example, piezoelectric injectors to spray coat opaque ink on the semiconductor substrate lateral edges as the individual ICs are conveyed through a pass-through. In addition, processes according to the present invention are independent of the techniques used to manufacture the light-sensitive ICs and, therefore, provide for increased packaging process flexibility and economy.

Method of preparing light-sensitive integrated circuits for packaging

Atomic oxygen, or a mixture of atomic oxygen and atomic nitrogen, is utilized in thermally oxidizing silicon to form a layer of silicon dioxide, or nitrogen-doped silicon dioxide, on a surface of the silicon. Use of atomic oxygen (or O &plus;N ) provides a better stoichiometric silicon dioxide structure with fewer dangling bonds than results from standard oxidation processes. The atomic oxygen (or O &plus;N ) may be generated within the oxidation furnace, for example by passing the gas through a heated ceramic material (e.g., Al O ) or by using internal UV radiation of the oxygen gas. Alternatively, the atomic oxygen (or O &plus;N ) may be generated at a remote source, for example in a plasma reactor, and then introduced to the oxidation furnace. Atomic chlorine can be generated and used prior to the oxidation step for pre-cleaning the silicon surface.

Thermal oxidation method utilizing atomic oxygen to reduce dangling bonds in silicon dioxide grown on silicon

A planarization process in which an organic film prevents oxide dishing during the chemical mechanical polishing step. In the planarization process an organic film having high CMP selectivity to silicon dioxide is spun over silicon dioxide. A patterned mask is then placed over the organic film and the exposed portions of the organic film are etched away. The remaining portions of the organic film prevent oxide dishing during chemical mechanical polishing because the high CMP selectivity of the organic film to silicon dioxide stops the etching before oxide dishing occurs. The organic film may then be oxygen ashed off the planarized surface if so desired.

Method of using organic material to enhance STI planarization or other planarization processes

A method for removing a resistive film formed on an electrode to increase the conductive contact area of the electrode positioned in a misaligned contact hole. The method comprises providing a substrate supporting an electrode layer. The electrode layer is etched to produce metal lines. During the processing of the metal lines, a resistive film is formed thereon. The resistive film is removed and a protective barrier is formed on the metal lines. A dielectric layer is formed on the substrate, including the metal lines. The dielectric layer is subsequently patterned to form contact holes or vias to expose a portion of the metal lines. The contact holes are filled with plugs such that a second electrode layer can be formed on the dielectric layer and the plugs.

Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects

Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be completely or partially removed to &ldquo;lift-off&rdquo; silicide stringers if formed. After silicide stringer removal, a dielectric layer, having a first portion and second portion that are selectively etchable with respect to one another, is deposited. A gate contact opening is formed in the dielectric layer where the opening is essentially the same dimension as the gate length. Alignment of the opening to the gate electrode is buffered by the thickness of the first portion of the dielectric layer, adjacent sidewalls of the gate electrode.

Semiconductor device with self aligned contacts having integrated silicide stringer removal and method thereof

A process for forming a via in a semiconductor device using a self-aligned tungsten pillar to connect upper and lower conductive layers separated by a dielectric. A Ti/TiN layer is formed on an underlying substrate layer, an aluminum-copper layer is formed on the Ti/TiN layer, a TiN layer is formed on the aluminum-copper layer and a tungsten layer is formed on the TiN layer. In one continuous etching step, the stack of tungsten, TiN, Al--Cu, Ti/TiN is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the substrate layer and the conductive stack. The wafer is then planarized to expose the top of the tungsten layer. The wafer is again patterned and the tungsten is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the tungsten pillar. An aluminum-copper layer is then formed on the overlying dielectric to make electrical contact to the exposed surface of the tungsten pillar. Since the etch of the upper aluminum-copper layer to form the upper interconnect pattern is highly selective to tungsten, the tungsten is not etched if there is misalignment of the upper metal mask.

Self-aligned interconnect using high selectivity metal pillars and a via

A method for solid state formation of diamond includes providing a diamond growth substrate, such as single-crystal silicon, forming on the diamond growth substrate an alloy of carbon and a metal which permits carbon to exist in a matrix therein, and causing carbon atoms from the alloy to precipitate on the diamond growth substrate in a diamond cubic lattice. The alloy may be an alloy of aluminum and carbon. The alloy is annealed in a hydrogen ambient to cause diffusion of hydrogen through the alloy to the surface of the substrate, providing a high concentration of hydrogen at the interface between the substrate and the alloy. The alloy is heated to cause carbon atoms in the alloy to diffuse through the alloy to the interface and form diamond.

Method for solid-state formation of diamond

A layer of silicon oxide is first formed on the silicon substrate. A mask is then formed on the oxide layer to define at least one surface region of the oxide that is not covered by the mask and a continuous strip of mask material that extends continuously around the unmasked oxide surface region. The mask is then used to etch the oxide surface region to expose an underlying substrate surface region and, thereby creating a continuous wall of oxide around the substrate surface region. The mask is then removed and oxygen ions are implanted into the silicon substrate to define a horizontal layer of oxide ions within the substrate. The wall of oxide surrounding the substrate surface region impairs the implant of oxygen ions beneath the wall such that a continuous substantially vertical wall of oxygen ions is formed in the substrate extending from the perimeter of the horizontal oxygen ion layer to the surface of the substrate. The substrate is then heat treated to cause the oxygen ions in the substrate to react with silicon to form silicon oxide that defines a silicon oxide island on all sides except the surface of the substrate, thereby forming an electrically isolated active device region.

Box isolation technique for integrated circuit structures

Growing community of inventors

Milpitas, CA, United States of America

Michael E Thomas