Michael D Steigerwalt

This inventor holds 16 USPTO granted patents and 1 published patent application, primarily in Silicon-On-Insulator Technology. Top assignees: International Business Machines Corporation, Globalfoundries Inc.. Active years: 2002-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Michael D Steigerwalt. Retrieved from https://idiyas.com/inventor/michael-d-steigerwalt

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 16 (Patent Applications = 1)

% Patents Active = 18.8

Average Co-Inventor Count = 5.0

ph-index = 7

Forward Citations = 368(Granted Patents)

Company Filing History:

16 out of 166,425

International Business Machines Corporation

where one patent can have more than one assignee

Years Active: 2002-2013

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Areas of Expertise:

Silicon-On-Insulator

Vertical Bipolar Transistor

Self-Aligned SiGe

Thin-Buried Oxide

Majority Carrier Accumulation

STI Formation

Trench Capacitor Cell

EPI Processing

Low-Substrate Bias

Deep Trench Etching

Floating Body Array Transistor

16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8598009 - Self-aligned embedded SiGe structure and method of manufacturing the same (2013-12-03),

2. 8232186 - Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure (2012-07-31),

3. 8222673 - Self-aligned embedded SiGe structure and method of manufacturing the same (2012-07-17),

4. 7911024 - Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof (2011-03-22),

5. 7763518 - Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof (2010-07-27),

6. 7691716 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation (2010-04-06),

7. 7485537 - Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness (2009-02-03),

8. 7394131 - STI formation in semiconductor device including SOI and bulk silicon regions (2008-07-01),

9. 7375410 - Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof (2008-05-20),

10. 7118986 - STI formation in semiconductor device including SOI and bulk silicon regions (2006-10-10),

11. 7115965 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation (2006-10-03),

12. 7115463 - Patterning SOI with silicon mask to create box at different depths (2006-10-03),

13. 6995094 - Method for deep trench etching through a buried insulator layer (2006-02-07),

14. 6964897 - SOI trench capacitor cell incorporating a low-leakage floating body array transistor (2005-11-15),

15. 6900092 - Surface engineering to prevent epi growth on gate poly during selective epi processing (2005-05-31),

Title: Michael D. Steigerwalt: Innovator in Semiconductor Technology

Introduction

Michael D. Steigerwalt is a prominent inventor based in Newburgh, NY (US), known for his significant contributions to semiconductor technology. With a total of 16 patents to his name, he has made remarkable advancements in the field, particularly in the development of innovative structures and manufacturing methods.

Latest Patents

Among his latest patents is the "Self-aligned embedded SiGe structure and method of manufacturing the same." This invention involves creating a low energy surface through a high-temperature anneal of trench surfaces adjacent to a gate stack. The semiconductor layer's material reflows during this process, resulting in a crystallographic surface at a non-orthogonal angle to the surface normal. This method allows for the selective growth of lattice mismatched semiconductor material in the source and drain regions of a transistor, enabling in-situ doping without increasing punch-through. Another notable patent is focused on "Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET." This patent outlines techniques for integrating reverse embedded silicon germanium (SiGe) on an NFET and a SiGe channel on a PFET, enhancing the performance of these devices.

Career Highlights

Michael has worked with leading companies in the semiconductor industry, including International Business Machines Corporation (IBM) and Globalfoundries Inc. His experience in these organizations has allowed him to refine his expertise and contribute to groundbreaking technologies.

Collaborations

Throughout his career, Michael has collaborated with notable professionals such as Herbert Lei Ho and Mahender Kumar. These partnerships have fostered innovation and have been instrumental in the development of his patented technologies.

Conclusion

Michael D. Steigerwalt's work in semiconductor technology exemplifies the spirit of innovation. His patents reflect a deep understanding of materials and manufacturing processes, positioning him as a key figure in the advancement of modern electronics.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: