The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2005

Filed:

Jun. 09, 2003
Applicants:

Karen A. Bard, Hopewell Junction, NY (US);

David M. Dobuzinsky, New Windsor, NY (US);

Herbert L. Ho, New Windsor, NY (US);

Mahendar Kumar, Fishkill, NY (US);

Denise Pendleton, Wappingers Falls, NY (US);

Michael D. Steigerwalt, Newburgh, NY (US);

Brian L. Walsh, New Paltz, NY (US);

Inventors:

Karen A. Bard, Hopewell Junction, NY (US);

David M. Dobuzinsky, New Windsor, NY (US);

Herbert L. Ho, New Windsor, NY (US);

Mahendar Kumar, Fishkill, NY (US);

Denise Pendleton, Wappingers Falls, NY (US);

Michael D. Steigerwalt, Newburgh, NY (US);

Brian L. Walsh, New Paltz, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/8242 ;
U.S. Cl.
CPC ...
Abstract

A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.


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