The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
Apr. 08, 2008
Herbert L. Ho, New Windsor, NY (US);
Mahender Kumar, Fishkill, NY (US);
Qiqing Ouyang, Yorktown Heights, NY (US);
Paul A. Papworth, Wappingers Falls, NY (US);
Christopher D. Sheraw, Wappingers Falls, NY (US);
Michael D. Steigerwalt, Newburgh, NY (US);
Herbert L. Ho, New Windsor, NY (US);
Mahender Kumar, Fishkill, NY (US);
Qiqing Ouyang, Yorktown Heights, NY (US);
Paul A. Papworth, Wappingers Falls, NY (US);
Christopher D. Sheraw, Wappingers Falls, NY (US);
Michael D. Steigerwalt, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a 'collector-less' silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.